1. Field of the Invention
This invention relates to a power semiconductor device and, more particularly, to a power MOSFET device
2. Description of the Related Art
In recent years, there has been a rapidly increasing demand for power MOSFET devices in a market of large current switching power supply devices with a high breakdown voltage, as well as in the market of switching power supply devices for mobile telecommunications devices including notebook-sized personal computers (PCs) so as to realize highly power-saving. Since power MOSFET devices are adapted to applications particularly in the field of power management circuits and safety circuits for lithium ion cells, they are required to provide a number of functional features including a low voltage drive capability that allows them to be used directly with the cell voltage, a low ON resistance and a reduced switching loss. These functional features can be realized by a reduced capacitance between the gate and the drain of the power MOSFET device. To meet these requirements, studies are made for applying horizontal element structures that have hitherto been mainly used for ICs to discrete elements in addition to the use of vertical element structures. With the use of the horizontal element structure, it is possible to reduce both the ON-resistance and the capacitance between the gate and the drain of a power MOSFET device.
FIG. 79 of the accompanying drawing is a schematic cross sectional view of a conventional vertical type power MOSFET device. With this vertical type power MOSFET device, an n−type epitaxial layer 102 is formed on an n+type semiconductor substrate 101 and a pair of p-type base layers 103a, 103b is formed on respective surface regions of the epitaxial layer 102 with a predetermined distance separating them. Then, n+type source regions 104a, 104b are formed respectively on surface regions of the p-type base layers 103a, 103b that are separated from a boundary between the epitaxial layer 102 and the p-type base layers 103a, 103b by a distance corresponding to the channel length. The n+type source regions 104a, 104b are located adjacent to respective p+type layers 105a, 105b which are used for connection to a power source. Subsequently, a gate electrode 106 is formed between the pair of source regions 104a, 104b to cover the surfaces of the base layers 103a, 103b and all the surface of the epitaxial layer 102 with a gate insulating film 107 interposed between them. Source electrodes 108a, 108b are formed on the respective surfaces of the p+type layers 105a, 105b so as to partly cover the surfaces of the source regions 104a, 104b. A drain electrode 109 is formed on the lower surface of the n+type semiconductor substrate 101.
FIG. 80 is a schematic cross sectional view of another conventional power MOSFET device, wherein a lateral element structure is applied to a discrete element in order to reduce the capacitance between the gate and the drain thereof. Referring to FIG. 80, an n−type epitaxial layer 202 is formed on an n+type semiconductor substrate 201 and a pair of p type base layers 203a, 203b is formed on respective surface regions of the epitaxial layer 202 with a predetermined distance separating them. Then, n+type source regions 204a, 204b are formed respectively on surface regions of the p type base layers 203a, 203b with a distance separated from a boundary between the epitaxial layer 202 and the base layers 203a, 203b corresponding to the channel length. The layers 204a, 204b are located adjacent to respective p+type layers 205a, 205b which are used for connection to a power source. N-type LDD layers 207a, 207b are formed on the surface of the epitaxial layer 202 between the pair of p type base layers 203a, 203b with a deep n+type sinker layer 206 interposed between them. The sinker layer 206 is so deep as to get to the n+type substrate 201. Then, between the paired source regions 204a, 204b and the corresponding paired LDD layers 207a, 207b, gate electrodes 208a, 208b are formed to cover the surfaces of the base layers 203a, 203b and those of the epitaxial layer 202 with gate insulating films 209a, 209b interposed between them respectively. Source electrodes 210a, 210b are formed respectively on the surfaces of the p+type layers 205a, 205b so as to partly cover the surfaces of the source regions 204a, 204b. A drain electrode 211 is formed on the lower surface of the n+type substrate 201.
The conventional vertical type power MOSFET device shown in FIG. 79 is accompanied by a problem of a large capacitance between the gate and the drain and a slow switching speed because the n−type epitaxial layer 102 and the gate electrode 106 are arranged oppositely over a large area with the gate insulating film 107 interposed between them.
On the other hand, the conventional horizontal type power MOSFET device shown in FIG. 80 has a problem that any effort for reducing the pitch of arrangement of elements, or the distance between the gate electrodes 208a, 208b faces the limit because the central sinker layer 206 is formed by diffusion and its surface width expands substantially as large as the distance between the surface and the n+type substrate 201. Accordingly, any attempt at reducing the ON-resistance per unit sectional area also faces a limit.